SOC DESIGN VERIFICATION ENGINEER

Company: Esperanto.ai
Location: Mountain View
Posted on: November 14, 2024

Job Description:

Esperanto delivers high-performance, energy-efficient, and innovative computing solutions that are the compelling choice for the most demanding AI and non-AI applications. The changing, computationally intensive workloads of the machine learning era mandate a new clean-sheet solution, without the baggage of existing legacy architectures, or the programmability limitations of overspecialized hardware. Esperanto leverages the simple, elegant, open standard RISC-V ISA along with leading-edge system architectures to deliver flexibility, scalability, performance, and energy-efficiency advantages.Responsibilities

• Create verification content including testplans, test bench components, directed and constrained random tests, and functional coverage
• Execute testplans to fully verify SoC component blocks
• Broader responsibilities may include supporting full-chip simulation, emulation, and post-silicon bring upQualifications

• Ability to clearly communicate across teams with multidisciplinary backgrounds
• 5+ years of experience in CPU, IP or SoC verification
• Knowledge of high-level verification flow methodology (testplan development, constrained random test generation and debug, coverage analysis and closure)
• Experience with a class-based testbench using System Verilog is required
• Knowledge of processors, cache, and cache coherence is required
• Experience with UVM/OVM is required
• BS/MS EENice to Have
  • Experience with Tcl is a plus
  • Experience with C and RISC-V assembly programming is a plus
  • Experience with Python, Perl, or other scripting languages is a plus
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Keywords: Esperanto.ai, Concord , SOC DESIGN VERIFICATION ENGINEER, Engineering , Mountain View, California